W949D6DB Datasheet, PDF (51/60 Pages) Winbond – Standard Self Refresh Mode

W949D6DB / W949D2DB
9.4 DC Characteristics
9.4.1 IDD Specification and Test Conditions (x16)
[Recommended Operating Conditions; Note 1-4]
PARAMETER
SYMBOL
TEST CONDITION
-5 -6 UNIT
Operating one bank
active-precharge current
Precharge power-down
standby current
Precharge power-down
standby current with
clock stop
Precharge non power-
down standby current
Precharge non power-
down standby current
with clock stop
Active power-down
standby current
Active power-down
standby current with
clock stop
Active non power-down
standby current
Active non power-down
standby current with
clock stop
Operating burst read
current
Operating burst write
current
Auto-Refresh Current
Deep Power-Down
current
IDD0
IDD2P
IDD2PS
IDD2N
IDD2NS
IDD3P
IDD3PS
IDD3N
IDD3NS
IDD4R
IDD4W
IDD5
IDD8^*4
tRC = tRCmin; tCK = tCKmin; CKE is HIGH; CS is
HIGH between valid commands; address inputs ^{40 38 mA}
are SWITCHING; data bus inputs are STABLE
all banks idle, CKE is LOW; CS is HIGH, tCK =
tCKmin; address and control inputs are
0.3 0.3 mA
SWITCHING; data bus inputs are STABLE
all banks idle, CKE is LOW; CS is HIGH, CK =
LOW, CK = HIGH; address and control inputs
0.3 0.3 mA
are SWITCHING; data bus inputs are STABLE
all banks idle, CKE is HIGH; CS is HIGH, tCK =
tCKmin; address and control inputs are
10 10 mA
SWITCHING; data bus inputs are STABLE
all banks idle, CKE is HIGH; CS is HIGH, CK =
LOW, CK = HIGH; address and control inputs
3 3 mA
are SWITCHING; data bus inputs are STABLE
one bank active, CKE is LOW; CS is HIGH,
tCK = tCKmin; address and control inputs are
SWITCHING; data bus inputs are STABLE
3 3 mA
one bank active, CKE is LOW; CS is HIGH, CK
= LOW, CK = HIGH; address and control inputs ^{3 3 mA}
are SWITCHING; data bus inputs are STABLE
one bank active, CKE is HIGH; CS is HIGH,
tCK = tCKmin; address and control inputs are
SWITCHING; data bus inputs are STABLE
25 25 mA
one bank active, CKE is HIGH; CS is HIGH,
CK = LOW, CK = HIGH; address and control
15 15 mA
inputs are SWITCHING; data bus inputs are
STABLE
one bank active; BL = 4; CL = 3; tCK = tCKmin;
continuous read bursts; IOUT = 0 mA; address
inputs are SWITCHING; 50% data change each
75 70
mA
burst transfer
one bank active; BL = 4; tCK = tCKmin;
continuous write bursts; address inputs are
SWITCHING; 50% data change each burst
55 50 mA
transfer
tRC = tRFCmin; tCK = tCKmin ; burst refresh; CKE
is HIGH; address and control inputs are
75 75 mA
SWITCHING; data bus inputs are STABLE
Address and control inputs are STABLE; data
bus inputs are STABLE
10 10 µA
- 51 -
Publication Release Date: Oct. 08, 2014
Revision: A01-003