W83194BR-603 Datasheet, PDF (7/26 Pages) Winbond – Winbond Clock Generator For INTEL P4 Springdale Series Chipset

W83194BR-603/W83194BG-603
CLOCK GEN. FOR INTEL P4 SPRINGDALE/PRESCOTT SERIES CHIPSET
5. PIN DESCRIPTION
BUFFER TYPE SYMBOL
IN
IN_tp120k
IN_td120k
OUT
OD
I/OD
#
*
&
DESCRIPTION
Input
Latched input at power up, internal 120kΩ pull up.
Latched input at power up, internal 120kΩ pull down.
Output
Open Drain
Bi-directional Pin, Open Drain.
Active Low
Internal 120kΩ pull-up
Internal 120 kΩ pull-down
5.1 Crystal I/O
PIN
PIN NAME
4
XIN
5
XOUT
TYPE
DESCRIPTION
IN
OUT
Crystal input with internal loading capacitors (18pF) and
feedback resistors.
Crystal output at 14.318MHz nominally with internal loading
capacitors (18pF).
5.2 CPU, SRC, 3V66 and PCI Clock Outputs
PIN
PIN NAME
42,39,41,38 CPUT [0:1]
CPUC [0:1]
45,44 CPUT_ITP
CPUC_ITP
36,35 SRCT, SRCC
30 3V66_0
RESET#
29,26
25
3V66_1:2
3V66_3
VCH_CLK
7
PCI_F0
FS2^&
TYPE
DESCRIPTION
OUT Low skew (< 250ps) differential clock outputs for host
frequencies of CPU
OUT 　 Differential clock outputs for host frequencies of CPU
OUT
OUT
OD
OUT
　 Differential clock outputs 100MHz/200MHz Select by for
SRC
　 3.3V 66MHz clock output (Default). Selected by MODE
latch input =0.
　 System reset signal when the watchdog is time out. This
pin will generate 250ms low phase when the watchdog
timer is timeout. Selected by MODE latch input =1.
　 3.3V 66MHz clock outputs.
OUT
OUT
OUT
　 3.3V 66MHz clock output (Default), Selected by Register
byte 3 bit 4 =0.
　 3.3V 48MHz clock output, Selected by Register byte 3 bit
4 =1.
　 3.3V PCI free running clock output.
IN_td120k Latched input for FS2 at initial power up for H/W selecting
the output frequency. This is internal 120K pull down.
Publication Release Date: March, 2006
-3-
Revision 0.7