W83194BR-603 Datasheet, PDF (12/26 Pages) Winbond – Winbond Clock Generator For INTEL P4 Springdale Series Chipset

W83194BR-603/W83194BG-603
CLOCK GEN. FOR INTEL P4 SPRINGDALE/PRESCOTT SERIES CHIPSET
7.3 Register 2: PCI Clock Register (1 = Enable, 0 = Stopped) (Default: FFh)
BIT
PIN NO PWD
DESCRIPTION
7
9
1 PCI_F2 output control.
6
8
1 PCI_F1 output control.
5
7
1 PCI_F0 output control.
4
-
1 Reserved
3
-
1 Reserved
2
19
1 PCI5 output control.
1
18
1 PCI4 output control.
0
15
1 PCI3 output control.
7.4 Register 3: PCI, 3V66 Clock Register (1 = Enable, 0 = Stopped) (Default: EFh)
BIT
PIN NO PWD
DESCRIPTION
7
14
1 PCI2 output control.
6
13
1 PCI1 output control.
5
12
1 PCI0 output control.
4
-
0 3V66_3 / VCH output select 1: VCH output, 0: 3V66 output (Default)
3
25
1 3V66_3 / VCH output control.
2
26
1 3V66_2 output control.
1
29
1 3V66_1 output control.
0
30
1 3V66_0 output control.
7.5 Register 4: 24_48MHz, 48MHz, REF, SRC Control Register (1 = Enable, 0 =
Stopped) (Default: BFh)
BIT
PIN NO PWD
DESCRIPTION
7
21
1 24_48MHz output control.
6
-
0 Reserved
5
22
1 48MHz output control.
4
-
1 Reserved
3
2
1 REF1 output control.
2
1
1 REF0 output control.
1
35,36
1 SRCT/C output control.
0
-
1 Reserved
-8-