W83194BR-603 Datasheet, PDF (18/26 Pages) Winbond – Winbond Clock Generator For INTEL P4 Springdale Series Chipset

W83194BR-603/W83194BG-603
CLOCK GEN. FOR INTEL P4 SPRINGDALE/PRESCOTT SERIES CHIPSET
7.17 Register 16: Control Register (Default: 24h)
BIT
NAME PWD
DESCRIPTION
7 INV_3V66
0 Invert the 3V66 phase, 0: Default, 1: Inverse
6 INV_PCI
0 Invert the PCI phase, 0: Default, 1: Inverse
5 SSKEW [2]
4 SSKEW [1]
3 SSKEW [0]
1 CPU to SRC skew control, Skew resolution is 340ps
0 ^{Expand the skew direction is same as}
0 ^{CPU_SRC_SKEW [2:0] setting}
2 PSKEW [2]
1 PSKEW [1]
0 PSKEW [0]
1 CPU to PCI skew control, Skew resolution is 340ps
0 ^{Expand the skew direction is same as}
0 ^{CPU_PCI_SKEW [2:0] setting}
7.18 Register 17: Slew rate Control Register (Default: 00h)
BIT
NAME PWD
DESCRIPTION
7 PCI_F2_S2
6 PCI_F2_S1
0 PCI_F2 slew rate control
0 11: Strong, 00: Weak, 10/01: Normal
5 PCI_F0_S2
4 PCI_F0_S1
0 PCI_F1 / PCI_F0 slew rate control
0 11: Strong, 00: Weak, 10/01: Normal
3 3V66_2_S2
2 3V66_2_S1
0 3V66_2 slew rate control
0 11: Strong, 00: Weak, 10/01: Normal
1 3V66_10_S2
0 3V66_10_S1
0 3V66_1 /3V66_0 slew rate control
0 11: Strong, 00: Weak, 10/01: Normal
7.19 Register 18: Slew rate Control Register (Default: 00h)
BIT
NAME PWD
DESCRIPTION
7 PCI_65_S2 0 PCI6, 5 slew rate control
6 PCI_65_S1 0 11: Strong, 00: Weak, 10/01: Normal
5 PCI_42_S2 0 PCI4, 3,2 slew rate control
4 PCI_42_S1 0 11: Strong, 00: Weak, 10/01: Normal
3 PCI_10_S2 0 PCI1, 0 slew rate control
2 PCI_10_S1 0 11: Strong, 00: Weak, 10/01: Normal
1 REF_S2
0 REF0, 1 slew rate control
0 REF_S1
0 11: Strong, 00: Weak, 10/01: Normal
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