W83194BR-603 Datasheet, PDF (15/26 Pages) Winbond – Winbond Clock Generator For INTEL P4 Springdale Series Chipset

W83194BR-603/W83194BG-603
CLOCK GEN. FOR INTEL P4 SPRINGDALE/PRESCOTT SERIES CHIPSET
7.11 Register 10: M/N Program Register (Default: BBh)
BIT
NAME
PWD
DESCRIPTION
7 N_DIV [9]
1 Programmable N divisor bit 9.
6 N3<6>
5 N3<5>
4 N3<4>
0 Programmable N3 divisor bit 6 ~0 for programmable SRC clocks.
1 Frequency range: 86.8M ~ 115.2M
1 ^{Resolution: 224K}
3 N3<3>
1
2 N3<2>
0
1 N3<1>
1
0 N3<0>
1
7.12 Register 11: Spread Spectrum Programming Register (Default: 0Bh)
BIT
NAME
7 SP_UP [3]
PWD
DESCRIPTION
0 Spread Spectrum Up Counter bit 3 ~ bit 0.
6 SP_UP [2]
0
5 SP_UP [1]
0
4 SP_UP [0]
0
3 SP_DOWN [3] 1 Spread Spectrum Down Counter bit 3 ~ bit 0
2 SP_DOWN [2] 0 2’s complement representation.
1 SP_DOWN [1] 1 ^{Ex: 1 -> 1111; 2 -> 1110; 7 -> 1001; 8 -> 1000}
0 SP_DOWN [0] 1
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Publication Release Date: March, 2006
Revision 0.7