W83194BR-603 Datasheet, PDF (19/26 Pages) Winbond – Winbond Clock Generator For INTEL P4 Springdale Series Chipset

W83194BR-603/W83194BG-603
CLOCK GEN. FOR INTEL P4 SPRINGDALE/PRESCOTT SERIES CHIPSET
7.20 Register 19: Control Register (Default: D2h)
BIT
NAME
PWD
DESCRIPTION
7 CPU1STOP_EN 1 Stop CPU1 clocks, 1: Enable stop feature, 0: Disable
6 CPU0STOP_EN 1 Stop CPU0 clocks, 1: Enable stop feature, 0: Disable
5 SRC_S2
0 SRC slew rate control
4 SRC_S1
1 11: Strong, 00: Weak, 10/01: Normal
3 INV_48MHz
0 Invert the 48MHz phase, 0: In phase with 24_48MHz
1: 180 degrees out of phase
2 48MHz_S2
0 48MHz/24_48MHz slew rate control
1 48MHz_S1
1 11: Strong, 00: Weak, 10/01: Normal
0 MODE
X Pin 30 Mode selection, 1: RESET# output, 0: 3V66_0 (Default)
Default value follow hardware trapping data on MODE^&/PCI0 pin.
7.21 Register 20: Watch dog timer Register (Default: 88h)
BIT
NAME PWD
DESCRIPTION
7 SRCF1
1 SRC frequency select, 00/01: 25MHz, 10: 100MHZ(Default), 11:
200MHz
6 WD_TIME [6] 0 Setting the down count depth. One bit resolution represents 250ms.
5 WD_TIME [5] 0 ^{Default time depth is 8*250ms = 2.0 second. If the watchdog timer is}
4 WD_TIME [4] 0 ^{counting, this register will return present down count value}
3 WD_TIME [3] 1
2 WD_TIME [2] 0
1 WD_TIME [1] 0
0 WD_TIME [0] 0
7.22 Register21: Control Register (Default: 00h)
BIT
NAME
7 Tri-state
6 Reserved
5 Reserved
4 FIX_SEL
3 SRCF0
2 ASEL_2
1 ASEL_1
0 ASEL_0
PWD
DESCRIPTION
0 Tri-state all output if set 1
0 Don’t modify it
0 Don’t modify it
0 3V66 output frequency select mode
0: Output frequency according to frequency selection table
1: Output frequency according to FIX frequency Reg21 bit 0~2
0 SRC frequency select, 0:100MHz. (Default), 1:200MHz
0 Asynchronous 3V66/PCI frequency table selection
0 ASEL_<2:0>
0
001: 66 / 33M
010: 75.43 / 37.7M
011: 88 / 44M
100: 88 / 44M
101: 66 / 33M
110: 75.43 / 33M
111: 88 / 33M
000: Clock from PLL1
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Publication Release Date: March, 2006
Revision 0.7