W83194BR-603 Datasheet, PDF (16/26 Pages) Winbond – Winbond Clock Generator For INTEL P4 Springdale Series Chipset

W83194BR-603/W83194BG-603
CLOCK GEN. FOR INTEL P4 SPRINGDALE/PRESCOTT SERIES CHIPSET
7.13 Register 12: Divisor and Step-less Enable Control Register: (Default: FBh)
BIT
NAME PWD
DESCRIPTION
7 Reserved
1 Reserved
6 DS9
5 DS5
1 Define the 3V66 divider ratio
1 ^{Table-2 integrate the all divider configuration}
4 Reserved
1 Reserved
3 Reserved
1
2 DS2
0 Define the CPU divider ratio
1 DS1
1 Refer to Table-2
0 DS0
1
Table-2 CPU, 3V66 divider ratio selection Table
LSB
3V66
Bit5
MSB
0
1
Bit2/
0
Div6
Div7
Bit9
1
Div10
Div12
00
Div2
Div8
CPU
Bit1, 0
01
10
Div3
Div4
Div8
Div8
11
Div6
Div8
7.14 Register 13: Divisor and Step-less Enable Control Register (Default: 0Fh)
BIT
NAME
PWD
DESCRIPTION
7 EN_MN_PROG
6 Reserved
0 0: Output frequency depend on frequency table
1: Program all clock frequency by changing M/N value
The equation is
VCO =14.318MHz*(N+4)/ M.
Once the watchdog timer timeout, the bit will be clear. Then the
frequency will be decided by hardware default FS<4:0> or desired
frequency select SAF_FREQ [4:0] depend on EN_SAFE_FREQ
(Reg0 - bit 0).
0 Reserved
5 Reserved
0 Reserved
4 Reserved
0 Reserved
3 IVAL<3>
1 Charge pump current selection
2 IVAL<2>
1
1 IVAL<1>
1
0 IVAL<0>
1
- 12 -