W83194BR-603 Datasheet, PDF (17/26 Pages) Winbond – Winbond Clock Generator For INTEL P4 Springdale Series Chipset

W83194BR-603/W83194BG-603
CLOCK GEN. FOR INTEL P4 SPRINGDALE/PRESCOTT SERIES CHIPSET
7.15 Register 14: Control Register (Default: 0Ah)
BIT
NAME PWD
DESCRIPTION
7 CPUT_DRI
0 CPUT output state in during POWER DOWN or Stop mode assertion.
1: Driven (2*Iref)
0: Tristate (Floating)
CPUC always tri-state (floating) in power down Assertion.
6 SRCT_DRI
0 SRC_T output state in during POWER DOWN or Stop mode assertion.
1: Driven (6*Iref => STOP mode)
(2*Iref => POWER DOWN)
0: Tristate (Floating)
SRC_C always tri-state (floating) in power down Assertion.
5 SPCNT [5]
4 SPCNT [4]
0 Spread Spectrum Programmable time, the resolution is 280ns. Default
0 ^{period is 11.8us}
3 SPCNT [3]
1
2 SPCNT [2]
0
1 SPCNT [1]
1
0 SPCNT [0]
0
7.16 Register 15: Control Register (Default: 2Ch)
BIT
NAME PWD
DESCRIPTION
7 INV_CPU
0 Invert the CPU phase, 0: Default, 1: Inverse
6 Reserved
0 Reserved
5 SPSP_TYPE 1 Spread spectrum implementation method
1: Pendulum type, 0: Original
4 SPSP1
0 Spread Spectrum type select.
3 SPSP0
1
00: Down 1%
01: Down 0.5%
10: Center +/- 0.5%
11: Center +/- 0.25%
2 ASKEW [2]
1 ASKEW [1]
0 ASKEW [0]
1 CPU to 3V66 skew control, Skew resolution is 340ps
0 ^{Expand the skew direction is same as}
0 ^{CPU_3V66_SKEW [2:0] setting}
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Publication Release Date: March, 2006
Revision 0.7