W83194BR-603 Datasheet, PDF (13/26 Pages) Winbond – Winbond Clock Generator For INTEL P4 Springdale Series Chipset

W83194BR-603/W83194BG-603
CLOCK GEN. FOR INTEL P4 SPRINGDALE/PRESCOTT SERIES CHIPSET
7.6 Register 5: Watchdog Control Register (Default: 02h)
BIT
NAME
PWD
DESCRIPTION
7 SEL24_48
X 24 / 48 MHz output selection, 1: 24 MHz.0: 48 MHz. (Default)
Default value follow hardware trapping data on SEL24_48# pin.
6 EN_WD
0 Program this bit =>
1: Enable Watchdog Timer feature.
0: Disable Watchdog Timer feature.
Read-back this bit =>
During timer count down the bit read back to 1.
If count to zero, this bit read back to 0.
5 WD_TIMEOUT 0 Read Back only. Timeout Flag. This bit is Read Only.
1: Watchdog has ever started and counts to zero.
0: Watchdog is restarted and counting.
4 SAF_FREQ [4] 0
3 SAF_FREQ [3] 0
2
SAF_FREQ [2]
0
These bits will be reloaded in Reg-0 to select frequency table. As the
watchdog is timeout and EN_SAFE_FREQ=1.
1 SAF_FREQ [1] 1
0 SAF_FREQ [0] 0
7.7 Register 6: Winbond Chip ID Register (Default: 60h) (Read Only)
BIT
NAME
PWD
DESCRIPTION
7
MAS_ID [1]
0 MASK definition for master body
6
MAS_ID [0]
1 *A****: 01, *B****: 10, *C****: 11, *D****:00
5
SUB_ID [1]
1 MASK definition for code body
4
SUB_ID [0]
0 *A****001: 01, *A****002: 10, *A****003: 11, *A****004:00
3 MAS_VER_ID [1] 0 MASK version definition for master body
2 MAS_VER_ID [0] 0 *A****001AA: 00, *A****001AB: 01,
*A****001AC: 10, *A****001AD: 11.
1 SUB_VER_ID [1] 0 MASK version definition for code body
0 SUB_VER_ID [0] 0 *A****001A: 00, *A****001B: 01 *A****001C: 10, *A****001D: 11
Publication Release Date: March, 2006
-9-
Revision 0.7