W83194BR-603 Datasheet, PDF (3/26 Pages) Winbond – Winbond Clock Generator For INTEL P4 Springdale Series Chipset

W83194BR-603/W83194BG-603
CLOCK GEN. FOR INTEL P4 SPRINGDALE/PRESCOTT SERIES CHIPSET
Table of Content-
1. GENERAL DESCRIPTION ......................................................................................................... 1
2. PRODUCT FEATURES .............................................................................................................. 1
3. PIN CONFIGURATION ............................................................................................................... 2
4. BLOCK DIAGRAM ...................................................................................................................... 2
5. PIN DESCRIPTION..................................................................................................................... 3
5.1 Crystal I/O.................................................................................................................................3
5.2 CPU, SRC, 3V66 and PCI Clock Outputs...............................................................................3
5.3 Fixed Frequency Outputs.........................................................................................................4
5.4 I2C Control Interface ................................................................................................................4
5.5 Power Management Pins.........................................................................................................5
5.6 IREF selects Function ..............................................................................................................5
5.7 Power Pins................................................................................................................................5
6. FREQUENCY SELECTION BY HARDWARE OR SOFTWARE ................................................ 6
7. I2C CONTROL AND STATUS REGISTERS .............................................................................. 7
7.1 Register 0: Frequency Select Register (Default = 10h) ..........................................................7
7.2 Register 1: CPU Clock Register (1 = Enable, 0 = Stopped) (Default: E2h) ...........................7
7.3 Register 2: PCI Clock Register (1 = Enable, 0 = Stopped) (Default: FFh).............................8
7.4 Register 3: PCI, 3V66 Clock Register (1 = Enable, 0 = Stopped) (Default: EFh)..................8
7.5 Register 4: 24_48MHz, 48MHz, REF, SRC Control Register (1 = Enable, 0 = Stopped)
(Default: BFh).........................................................................................................................................8
7.6 Register 5: Watchdog Control Register (Default: 02h)............................................................9
7.7 Register 6: Winbond Chip ID Register (Default: 60h) (Read Only) ........................................9
7.8 Register 7: Winbond Chip ID Register (Default: 70h) (Read Only) ......................................10
7.9 Register 8: M/N Program Register (Default: 90h) .................................................................10
7.10 Register 9: M/N Program Register (Default: 7Ah).................................................................10
7.11 Register 10: M/N Program Register (Default: BBh) ..............................................................11
7.12 Register 11: Spread Spectrum Programming Register (Default: 0Bh) ................................11
7.13 Register 12: Divisor and Step-less Enable Control Register: (Default: FBh) .......................12
7.14 Register 13: Divisor and Step-less Enable Control Register (Default: 0Fh) ........................12
7.15 Register 14: Control Register (Default: 0Ah).........................................................................13
7.16 Register 15: Control Register (Default: 2Ch).........................................................................13
7.17 Register 16: Control Register (Default: 24h) .........................................................................14
7.18 Register 17: Slew rate Control Register (Default: 00h).........................................................14
7.19 Register 18: Slew rate Control Register (Default: 00h).........................................................14
7.20 Register 19: Control Register (Default: D2h).........................................................................15
7.21 Register 20: Watch dog timer Register (Default: 88h) ..........................................................15
- II -