W972GG8JB-3-TR Datasheet, PDF (59/87 Pages) Winbond – 32M 8 BANKS 8 BIT DDR2 SDRAM

W972GG8JB
CLK
CLK
V_DDQ
tIS
tIH
tIS
tIH
V_IH(ac)min
V_IH(dc)min
DC to VREF
region
V_REF(dc)
V_IL(dc)max
tangent
line
tangent
line
nominal
line
nominal ^{DC to VREF}
line
region
V_IL(ac)max
V_SS
ΔTR
ΔTF
Hold Slew Rate
Rising Signal
=
tangent line[V_REF(dc) - V_IL(dc)max]
ΔTR
Hold Slew Rate ^{tangent line[VIH(dc)min - VREF(dc)]}
Falling Signal ⁼
ΔTF
Figure 23 – Illustration of tangent line for tIH
- 59 -
Publication Release Date: Dec. 03, 2012
Revision A03