W972GG8JB-3-TR Datasheet, PDF (5/87 Pages) Winbond – 32M 8 BANKS 8 BIT DDR2 SDRAM

W972GG8JB
4. KEY PARAMETERS
SYM.
SPEED GRADE
Bin(CL-tRCD-tRP)
Part Number Extension
@CL = 7
@CL = 6
tCK(avg) Average clock period
@CL = 5
@CL = 4
@CL = 3
tRCD
tRP
tRC
tRAS
IDD0
IDD1
IDD4R
IDD4W
IDD5B
IDD6
IDD7
Active to Read/Write Command Delay Time
Precharge to Active Command Period
Active to Ref/Active Command Period
Active to Precharge Command Period
Operating one bank active-precharge current
Operating one bank active-read-precharge current
Operating burst read current
Operating burst write current
Burst refresh current
Self refresh current (TCASE ≤ 85°C)
Operating bank interleave read current
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Min.
Min.
Min.
Max.
Max.
Max.
Max.
Max.
Max.
Max.
DDR2-1066
7-7-7
-18
1.875 nS
7.5 nS
2.5 nS
7.5 nS
3 nS
7.5 nS
3.75 nS
7.5 nS


13.125 nS
13.125 nS
58.125 nS
45 nS
85 mA
85 mA
165 mA
145 mA
175 mA
12 mA
220 mA
DDR2-800
5-5-5/6-6-6
-25/25I


2.5 nS
8 nS
2.5 nS
8 nS
3.75 nS
8 nS
5 nS
8 nS
12.5 nS
12.5 nS
57.5 nS
45 nS
72 mA
80 mA
135 mA
120 mA
160 mA
12 mA
200 mA
DDR2-667
5-5-5
-3




3 nS
8 nS
3.75 nS
8 nS
5 nS
8 nS
15 nS
15 nS
60 nS
45 nS
69 mA
75 mA
120 mA
110 mA
150 mA
12 mA
180 mA
Publication Release Date: Dec. 03, 2012
-5-
Revision A03