W972GG8JB-3-TR Datasheet, PDF (58/87 Pages) Winbond – 32M 8 BANKS 8 BIT DDR2 SDRAM

W972GG8JB
CLK
CLK
V_DDQ
tIS
tIH
V_IH(ac)min
V_IH(dc)min
DC to VREF
region
V_REF(dc)
V_IL(dc)max
nominal
slew rate
V_IL(ac)max
tIS
tIH
nominal
slew rate
DC to VREF
region
V_SS
Hold Slew Rate ^VREF(dc) ^{- V}IL(dc)max
Rising Signal ⁼
ΔTR
ΔTR
ΔTF
Hold Slew Rate ^VIH(dc)min ^{- V}REF(dc)
Falling Signal ⁼
ΔTF
Figure 22 – Illustration of nominal slew rate for tIH
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Publication Release Date: Dec. 03, 2012
Revision A03