W972GG8JB-3-TR Datasheet, PDF (57/87 Pages) Winbond – 32M 8 BANKS 8 BIT DDR2 SDRAM

W972GG8JB
CLK
CLK
V_DDQ
tIS
tIH
tIS
tIH
V_IH(ac)min
VREF to AC
region
V_IH(dc)min
nominal
line
V_REF(dc)
tangent
line
tangent
line
V_IL(dc)max
V_IL(ac)max
nominal
line
V_SS
ΔTF
VREF to AC
region
ΔTR
Setup Slew Rate ^{tangent line[VIH(ac)min - VREF(dc)]}
Rising Signal ⁼
ΔTR
Setup Slew Rate ^{tangent line[V}REF(dc) ^{- V}IL(ac)max^]
Falling Signal ⁼
ΔTF
Figure 21 – Illustration of tangent line for tIS
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Publication Release Date: Dec. 03, 2012
Revision A03