W741C260 Datasheet, PDF (52/92 Pages) Winbond – 4-BIT MICROCONTROLLER

W741C260
Instruction Set Table 2, continued
CLR DIVR0
Reset the last 4 bits of the DIVideR0
Machine Code:
Machine Cycle:
Operation:
Description:
CLR EVF, #I
00010111
00000000
1
Reset the last 4 bits of the Divider0
When this instruction is executed, the last 4 bits of the Divider0 (14 bits)
are reset.
Clear EVent Flag
Machine Code:
Machine Cycle:
Operation:
Description:
01000000
I7 I6 I5 I4 I3 I2 I1 I0
1
Clear event flag
The condition corresponding to the data specified by I7 to I0 is controlled.
I0 to I8 Mode after execution of instruction
I0 = 1 EVF0 caused by overflow from the Divider0 is reset.
I1 = 1 EVF1 caused by underflow from the Timer 0 is reset.
I2 = 1 EVF2 caused by signal change on port RC is reset.
I3 = 1 Reserved
I4 = 1 EVF4 caused by overflow from the Divider1 is reset.
I5, I6 Reserved
I7 = 1 EVF7 caused by underflow from the Timer 1 is reset.
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