W741C260 Datasheet, PDF (18/92 Pages) Winbond – 4-BIT MICROCONTROLLER

W741C260
Hold Mode Release Enable Flag (HEF)
The hold mode release enable flag is organized as an 8-bit binary register (HEF.0 to HEF.7). The
HEF is used to control the hold mode release conditions. It is controlled by the MOV HEF, #I
instruction. The bit descriptions are as follows:
76543210
HEF w
w
www
Note: W means write only.
HEF.0 = 1 Overflow from the Divider 0 causes hold mode to be released.
HEF.1 = 1 Underflow from Timer 0 causes hold mode to be released.
HEF.2 = 1 Signal change on port RC causes hold mode to be released.
HEF.3 Reserved
HEF.4 = 1 Overflow from the Divider 1 causes hold mode to be released.
HEF.5 & HEF.6 are reserved.
HEF.7 = 1 Underflow from Timer 1 causes hold mode to be released.
Port Enable Flag (PEF)
The port enable flag is organized as 4-bit binary register (PEF.0 to PEF.3). Before port RC may be
used to release the hold mode or preform interrupt function, the content of the PEF must be set first.
The PEF is controlled by the MOV PEF, #I instruction. The bit descriptions are as follows:
3210
PEF w w w w
Note: W means write only.
PEF.0: Enable/disable the signal change on pin RC.0 to release hold mode or perform interrupt.
PEF.1: Enable/disable the signal change on pin RC.1 to release hold mode or perform interrupt.
PEF.2: Enable/disable the signal change on pin RC.2 to release hold mode or perform interrupt.
PEF.3: Enable/disable the signal change on pin RC.3 to release hold mode or perform interrupt.
Hold Mode Release Condition Flag (HCF)
The hold mode release condition flag is organized as a 8-bit binary register (HCF0 to HCF7). It
indicates by which interrupt source the hold mode has been released, and is loaded by hardware. The
HCF can be read out by the MOVA R, HCFL and MOVA R, HCFH instructions. When any of the HCF
bits is "1," the hold mode will be released and the HOLD instruction is invalid. The HCF can be reset
by the CLR EVF,#I (EVF.n = 0) or MOV HEF,#I (HEF.n = 0) instructions. When EVF or HEF have
been reset, the corresponding bit of HCF is reset simultaneously. The bit descriptions are as follows:
76543210
HCF
RR
RRR
Note: R means read only.
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