W9412G6JH Datasheet, PDF (49/53 Pages) Winbond – 2M  4 BANKS  16 BITS DDR SDRAM

W9412G6JH
11.21 4 Bank Interleave Read Operation (CL = 2, BL = 2)
CLK
CLK
CMD ACTa
DQS
DQ
tRRD
tRRD
ACTb
tRCD(a)
tRAS(a)
tRC(a)
tRRD
tRRD
ACTc READAa ACTd READAb ACTa READAc
tRCD(b)
tRAS(b)
tRP
tRCD(c)
tRAS(c)
tRCD(d)
tRAS(d)
Preamble
CL(a)
Postamble Preamble
CL(b)
Q0a Q1a
Q0b Q1b
ACTa/b/c/d : Bank Act. CMD of bank a/b/c/d
READAa/b/c/d : Read with Auto Pre.CMD of bank a/b/c/d
APa/b/c/d : Auto Pre. of bank a/b/c/d
APa
APb
11.22 4 Bank Interleave Read Operation (CL = 2, BL = 4)
CLK
CLK
tRRD
tRRD
tRC(a)
tRRD
tRRD
CMD
ACTa
DQS
DQ
ACTb READAa
tRCD(a)
tRAS(a)
ACTc READAb ACTd READAc ACTa
tRCD(b)
tRAS(b)
tRCD(c)
tRAS(c)
tRP(a)
tRCD(d)
tRAS(d)
READAd
Preamble
CL(a)
CL(b)
CL(c)
Q0a Q1a Q0a Q1a Q2a Q3a Q0b Q1b Q2b Q3b
ACTa/b/c/d : Bank Act. CMD of bank a/b/c/d
READAa/b/c/d : Read with Auto Pre.CMD of bank a/b/c/d
APa/b/c/d : Auto Pre. of bank a/b/c/d
APa
APb
APc
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Publication Release Date: Nov. 29, 2011
Revision A03