W9412G6JH Datasheet, PDF (44/53 Pages) Winbond – 2M  4 BANKS  16 BITS DDR SDRAM

W9412G6JH
11.11 Read Interrupted by Read (CL = 2, BL = 2, 4, 8)
CLK
CLK
CMD
ADD
ACT
tRCD
Row Address
READ A
READ B
READ C
READ D
READ E
tCCD
tCCD
tCCD
tCCD
COl,Add,A Col,Add,B Col,Add,C Col,Add,D Col,Add,E
DQS
DQ
QA0 QA1 QB0 QB1 QC0
11.12 Burst Read Stop (BL = 8)
CLK
CLK
CMD
READ
BST
CAS Latency = 2
DQS
DQ
CAS Latency
Q0 Q1 Q2 Q3 Q4 Q5
CAS Latency = 3
DQS
DQ
CAS Latency
Q0 Q1 Q2 Q3 Q4 Q5
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Publication Release Date: Nov. 29, 2011
Revision A03