W9412G6JH Datasheet, PDF (27/53 Pages) Winbond – 2M  4 BANKS  16 BITS DDR SDRAM

W9412G6JH
AC Characteristics and Operating Condition, continued
SYM.
PARAMETER
-4
MIN. MAX.
tWPRE DQS Write Preamble Time
0.25
tWPST DQS Write Postamble Time
0.4 0.6
tDQSS
Write Command
Transition
to
First
DQS
Latching _0.85
1.15
tIS Input Setup Time (fast slew rate)
0.6
tIH Input Hold Time (fast slew rate)
0.6
tIS Input Setup Time (slow slew rate)
0.7
tIH Input Hold Time (slow slew rate)
0.7
tIPW
Control & Address Input Pulse Width (for each
input)
2.2
Data-out High-impedance Time from
tHZ
0.7
CLK, CLK
-5/-5I/-5K
MIN. MAX.
0.25
0.4 0.6
0.75 1.25
0.6
0.6
0.7
0.7
2.2
0.7
-6I
MIN. MAX.
0.25
0.4 0.6
0.75 1.25
0.75
0.75
0.8
0.8
2.2
0.7
UNIT NOTES
tCK
11
19, 21-23
19, 21-23
20-23
20-23
nS
tLZ _{Data-out Low-impedance Time from CLK, CLK} -0.7 0.7 -0.7 0.7 -0.7 0.7
tT(SS) SSTL Input Transition
0.5 1.5 0.5 1.5 0.5 1.5
tWTR Internal Write to Read Command Delay
2
2
1
tCK
tXSNR Exit Self Refresh to non-Read Command
72
75
75
nS
tXSRD Exit Self Refresh to Read Command
200
200
200
tCK
tREFi Refresh Interval Time (4K/64mS)
15.6
15.6
15.6 µS
17
tREFiA Refresh Interval Time (4K/16mS)*
-
3.9
-
µS
17
tMRD Mode Register Set Cycle Time
8
10
12
nS
* When -5K speed grade operation at 85°C < TA ≤ 105°C, increasing 4K Auto Refresh commands in frequency to a 16 mS
period.
9.7 AC Test Conditions
PARAMETER
Input High Voltage (AC)
Input Low Voltage (AC)
Input Reference Voltage
Termination Voltage
Differential Clock Input Reference Voltage
Input Difference Voltage. CLK and CLK Inputs (AC)
Output Timing Measurement Reference Voltage
SYMBOL
VIH
VIL
VREF
VTT
VR
VID (AC)
VOTR
VALUE
VREF + 0.31
VREF - 0.31
0.5 x VDDQ
0.5 x VDDQ
Vx (AC)
1.5
0.5 x VDDQ
UNIT
V
V
V
V
V
V
V
- 27 -
Publication Release Date: Nov. 29, 2011
Revision A03