W9412G6JH Datasheet, PDF (48/53 Pages) Winbond – 2M  4 BANKS  16 BITS DDR SDRAM

W9412G6JH
11.19 2 Bank Interleave Read Operation (CL = 2, BL = 2)
CLK
CLK
CMD
ACTa
tRRD
tRC(a)
tRC(b)
ACTb
tRCD(a)
tRAS(a)
READAa
tRCD(b)
tRAS(b)
READAb
ACTa
tRP(a)
tRRD
tRP(b)
ACTb
DQS
DQ
Preamble Postamble Preamble
CL(a)
CL(b)
Postamble
Q0a Q1a
Q0b Q1b
ACTa/b : Bank Act. CMD of bank a/b
READAa/b : Read with Auto Pre.CMD of bank a/b
APa/b : Auto Pre. of bank a/b
APa
APb
11.20 2 Bank Interleave Read Operation (CL = 2, BL = 4)
CLK
CLK
CMD
DQS
DQ
ACTa
tRRD
tRC(a)
tRC(b)
ACTb READAa
READAb
tRCD(a)
tRAS(a)
tRCD(b)
tRAS(b)
tRP(a)
ACTa
tRRD
tRP(b)
ACTb
Preamble
CL(a)
CL(b)
Postamble
Q0a Q1a Q2a Q3a Q0b Q1b Q2b Q3b
ACTa/b : Bank Act. CMD of bank a/b
READAa/b : Read with Auto Pre.CMD of bank a/b
APa/b : Auto Pre. of bank a/b
APa
APb
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Publication Release Date: Nov. 29, 2011
Revision A03