W9412G6JH Datasheet, PDF (23/53 Pages) Winbond – 2M  4 BANKS  16 BITS DDR SDRAM

W9412G6JH
9. ELECTRICAL CHARACTERISTICS
9.1 Absolute Maximum Ratings
PARAMETER
SYMBOL
RATING
UNIT
Voltage on any pin relative to VSS
VIN, VOUT
-0.5 ~ VDDQ + 0.5
V
Voltage on VDD/VDDQ supply relative to VSS
VDD, VDDQ
-1 ~ 3.6
V
Operating Temperature (-4/-5)
TOPR
0 ~ 70
°C
Operating Temperature (-5I/-6I)
TOPR
-40 ~ 85
°C
Operating Temperature (-5K)
TOPR
-40 ~ 105
°C
Storage Temperature
TSTG
-55 ~ 150
°C
Soldering Temperature (10s)
TSOLDER
260
°C
Power Dissipation
PD
1
W
Short Circuit Output Current
IOUT
50
mA
Note: Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device.
This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in
the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect reliability.
9.2 Recommended DC Operating Conditions
(TA = 0 to 70°C for -4/-5, TA = -40 to 85°C for -5I/-6I, TA = -40 to 105°C for -5K)
SYM.
PARAMETER
MIN.
TYP.
VDD Power Supply Voltage (for -5/-5I/-5K/-6I)
2.3
2.5
VDD Power Supply Voltage (for -4)
2.4
-
VDDQ I/O Buffer Supply Voltage (for -5/-5I/-5K/-6I)
2.3
2.5
VDDQ I/O Buffer Supply Voltage (for -4)
2.4
-
VREF Input reference Voltage
0.49 x VDDQ 0.50 x VDDQ
VTT Termination Voltage (System)
VREF - 0.04
VREF
VIH (DC) Input High Voltage (DC)
VREF + 0.15
-
VIL (DC) Input Low Voltage (DC)
-0.3
-
VICK (DC) Differential Clock DC Input Voltage
-0.3
-
VID (DC)
Input Differential Voltage.
CLK and CLK inputs (DC)
0.36
-
MAX.
2.7
2.7
2.7
2.7
0.51 x VDDQ
VREF + 0.04
VDDQ + 0.3
VREF - 0.15
VDDQ + 0.3
VDDQ + 0.6
VIH (AC)
VIL (AC)
VID (AC)
Input High Voltage (AC)
Input Low Voltage (AC)
Input Differential Voltage.
CLK and CLK inputs (AC)
VREF + 0.31
-
-
-
-
VREF - 0.31
0.7
-
VDDQ + 0.6
VX (AC) Differential AC input Cross Point Voltage
VDDQ/2 - 0.2
-
VDDQ/2 + 0.2
VISO (AC) Differential Clock AC Middle Point
VDDQ/2 - 0.2
-
VDDQ/2 + 0.2
Notes: VIH (DC) and VIL (DC) are levels to maintain the current logic state.
VIH (AC) and VIL (AC) are levels to change to the new logic state.
UNIT
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
NOTES
2
2
2
2
2, 3
2, 8
2
2
15
13, 15
2
2
13, 15
12, 15
14, 15
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Publication Release Date: Nov. 29, 2011
Revision A03