W9812G6IH Datasheet, PDF (26/42 Pages) Winbond – high-speed synchronous dynamic random access memory (SDRAM)

W9812G6IH
11.6 Interleaved Bank Write (Burst Length = 8, Auto-precharge)
CLK
CS
RAS
CAS
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
tRC
tRAS
tRP
tRAS
WE
BS0
BS1
A10
RAa
tRCD
A0-A9
RAa
A11
DQM
CKE
DQ
CAx
ax0 ax1
tRRD
Bank #0 Active
Bank #1
Bank #2
Idle
Bank #3
Write
RBb
tRCD
RBb
CBy
RAb
tRCD
RAc
CAz
ax4 ax5 ax6 ax7 by0 by1 by2 by3
tRRD
Active
AP*
Write
* AP is the internal precharge start timing
by4 by5 by6 by7 CZ0 CZ1
CZ2
Active
Write
AP*
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Publication Release Date:Jun. 05, 2008
Revision A03