W9812G6IH Datasheet, PDF (24/42 Pages) Winbond – high-speed synchronous dynamic random access memory (SDRAM)

W9812G6IH
11.4 Interleaved Bank Read (Burst Length = 8, CAS Latency = 3, Auto-precharge)
CLK
CS
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
tRC
RAS
CAS
WE
BS0
BS1
tRCD
A10 _RAa
tRAS
tRP
tRAS
tRAS
tRP
RBb
tRCD
tRCD
RAc
A0-A9, RAa
CAx
A11
DQM
RBb
CBy
RAc
CAz
CKE
DQ
Bank #0 Active
Bank #1
Bank #2
Idle
Bank #3
tCAC
tCAC
ax0 ax1 ax2 ax3 ax4 ax5 ax6 ax7 by0 by1
tRRD
Read
Active
tRRD
AP*
Read
Active
* AP is the internal precharge start timing
tCAC
by4 by5 by6
CZ0
Read
AP*
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Publication Release Date:Jun. 05, 2008
Revision A03