TMPR4938 Datasheet, PDF (693/716 Pages) Toshiba Semiconductor – 64-Bit TX System RISC TX49 Family

Chapter 24 Notes on Use of TMPR4938
24. Notes on Use of TMPR4938
24.1 Notes on TX49/H3 Core
• Restriction on detect of the Bus errors when a data cycle generated by load instruction.
[Restriction]
Error notification to the TX49/H3 Core using Bus errors is not enabled or Executing a SYNC
instruction immediately after the preceding load instruction.
[Violation]
When a Bus error exception (DBE) occurs during a data Read cycle generated by a preceding load
instruction and an exception with a higher priority than the Bus error exception (DBE) occurs in a
subsequently executed instruction, the exception of the subsequent instruction is processed first and Bus
error exceptions (DBE) are no longer detected.
<Conditions>
The TX49/H3 Core has a non-blocking load function. With this function, the instruction that follows
the preceding load instruction is executed without stalling if it is not dependent on the preceding load
instruction.
When reading the data from the preceding load instruction and a Bus Error exception (DBE) occurs
and an exception (see the following table for the priority order when consecutive instructions issue
multiple exceptions at the same timing) with a higher priority than the Bus Error exception (DBE) of
the subsequently executed instruction occurs, the exception that the subsequent instruction issued is
processed before the Bus Error exception (DBE) and Bus Error exceptions (DBE) can no longer be
detected.
Priority Order for Exceptions Issued at the Same Timing
Priority Sequence (High)
Cold Reset
Soft Reset
NMI
Bus Error (IBE)
Ov,Tr,Sys,Bp,RI,CpU,FPE
Address Error (AdEL/AdES)
TLB Refill (TLBL/TLBS)
TLB Invalid (TLBL/TLBS)
TLB Modify (TLBL/TLBS)
Bus Error (DBE)
Interrupt
Address Error (AdEL)
TLB Refill (TLBL)
TLB Invalid (TLBL)
Instruction Fetch
Data Access
Data Access
Data Access
Data Access
Data Access
Instruction Fetch
Instruction Fetch
Instruction Fetch
Detected
PipeStage
M
M
M
M
M
M
M
M
M
M
M
E
E
E
Instruction synchronous
or asynchronous
Async
Async
Async
Async
Sync
Sync
Sync
Sync
Sync
Async
Async
Sync
Sync
Sync
Note: The table above differs from Table 11-3 (Priority Order when the Same Instruction Issues Multiple
Exceptions at the Same Timing) on page 11-2 of the “TX49/H2, H3, H4 Core Architecture”.
24-1