TMPR4938 Datasheet, PDF (584/716 Pages) Toshiba Semiconductor – 64-Bit TX System RISC TX49 Family

Chapter 16 Ethernet Controller
Bit(s)
7
6
5
4
3:0
Mnemonic
IntTx
Paused
TxDefer
ExColl
TxColl
Field Name
Transmission
Interrupt
Transmitter Paused
Transmission
Deferred
Excessive Collisions
Transmission
Collision Count
Description
IntTx (Default: 0, R)
This bit is set when interrupt conditions specified by the Transmission Control
Register are met in a packet transmission.
Paused (Default: 0, R)
This bit is set if transmission is paused after the current packet ends.
TxDefer (Default: 0, R)
Indicates that a packet was kept waiting due to transmission delay.
ExColl (Default: 0, R)
This bit is set if collisions occur 16 times in the same packet. Instead of
transmitting that packet, processing of the next packet transmission starts.
TxColl (Default: 0, R)
Number of collisions that occurred when transmitting one packet.
Figure 16.4.35 Transmission Status Register (2/2)
Software resets initialize the Transmission Status Register to 0x00_0000. Also, this register is
cleared at the beginning of each transmission packet.
The Transmission Status flag is set each time the applicable event occurs. Also, an interrupt
occurs if the corresponding bit of the Transmission Control Register is set.
The lower 5 bits of the Transmission Status Register indicate the collision count of the packet.
In other words, when ExColl=1, TxColl becomes 0. If TxColl is not 0, then ExColl=0.
The MAX_DEFERRAL time is 0.24288 ms for 100 Mbps and 2.42880 ms for 10 Mbps. If the
TxMCast bit (bit 17) and the TxBCast bit (bit 18) are both "0", they indicate that a unicast packet
was transmitted.
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