TMPR4938 Datasheet, PDF (396/716 Pages) Toshiba Semiconductor – 64-Bit TX System RISC TX49 Family

Chapter 11 Serial I/O Port
Bit Mnemonic Field Name
Description
Read/Write
7
RDIS
Reception Data Receive DMA/Interrupt Status (Default: 0)
R/W0C
Full
This bit is set when valid data of the amount set by the Receive FIFO
Request Trigger Level (RDIL) of the FIFO Control register (SIFCR) is stored
in the Receive FIFO.
6
STIS
Status Change Status Change Interrupt Status (Default: 0)
R/W0C
This bit is set when at least one of the interrupt statuses selected by the
Status Change Interrupt Condition field (STIE) of the DMA/Interrupt Control
Register (SIDICR) becomes “1”.
5
Reserved
⎯
4:0
RFDN
Reception Data Receive FIFO Data Number (Default: 00000)
R
Stage Status
This field indicates how many stages of reception data remain in the
Receive FIFO
(0 – 16 stages).
Figure 11.4.3 DMA/Interrupt Status Register (2/2)
11-18