TMPR4938 Datasheet, PDF (565/716 Pages) Toshiba Semiconductor – 64-Bit TX System RISC TX49 Family

Chapter 16 Ethernet Controller
16.4.3.2 Transmission Frame Pointer Register 0x04
31
16
Addr
R/W
: Type
0x0000
: Default
15
4
3
2
1
0
Adrr
Reserved
EOL
R/W
0x000
R/W : Type
1 : Default
Bit(s)
31:4
3:1
0
Mnemonic
Field Name
Address
EOL
Reserved
End of List
Description
Addr (Default: 0x000_0000, R/W)
Retains the address of the first frame descriptor to be
transmitted.
EOL (Default: 1, R/W)
When this bit is set to “1”, the Address field is ignored. The
Ethernet Controller waits for the system to clear it.
Figure 16.4.20 Transmission Frame Pointer Register
Software resets initialize the Transmission Frame Pointer Register to 0x0000_0001.
Software resets set the EOL bit to “1”. To enable polling of a transmission or the packet to be
transmitted, the system has to set this register in a properly initialized frame descriptor. The
address has to be aligned to a 16-Byte boundary. Therefore, bits 0-3 must be “0”.
For information on polling control methods, see the description in 16.4.3.4 Transmission
Polling Control Register.
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