TMPR4938 Datasheet, PDF (255/716 Pages) Toshiba Semiconductor – 64-Bit TX System RISC TX49 Family

Chapter 9 SDRAM Controller
Bit Mnemonic Field Name
Description
Read/Write
24
23
22:18
17
16
15
14
13:12
11:0
ACE
PDAE
RC
CASL
DRB
DA
SWB
—
RP
Advanced CKE
Power Down
Auto Entry
Refresh Counter
CAS Latency
Data Read
Bypass
Active Command
Delay
Slow Write Burst
—
Refresh Period
Advanced CKE enable (Default: 0)
Enabling this function makes the timing at which CKE changes one cycle
earlier.
0: Disable
1: Enable
Power Down Auto Entry Enable (Default: 0)
Enabling this function makes CKE become “L” while the SDRAMC is in the
Idle state. When refresh, memory access, or command execution is
performed, CKE automatically becomes “H”, the requested operation is
performed, then CKE returns to “L” when the operation is complete.
0: Disable
1: Enable
Refresh Counter (Default: 000000)
This counter is decremented at each refresh. If the refresh circuit is
activated and a value other than “0” is loaded, this field becomes a down
counter that stops at “0”. A value other than “0” must be reloaded to start
the countdown again. This is used during memory initialization.
CAS Latency (t_CASL) (Default: 1)
Specifies the CAS latency.
0: 2 t_CK
1: 3 t_CK
Data Read Bypass (Default: 0)
Selects the Data Read path used.
0: Data Read latches to the register using the feedback clock.
1: Data Read bypasses the feedback clock latch.
Delay Activate (t_DA) (Default: 1)
Specifies the delay from the row address to the bank active command.
Setting this bit to “1” sets up the row address two cycles before the active
command is executed.
0: 0 t_CK
1: 1 t_CK
Slow Write Burst (t_SWB) (Default: 1)
Specifies whether to perform Slow Write Burst.
0: Burst Write occurs at each 1 t_CK
1: Burst Write occurs at each 2 t_CK
Reserved
Refresh Period (Default: 0x30c)
Specifies the clock cycle count that generates the refresh cycle. Refresh is
only enabled when at least one SDRAM channel is enabled. Please
program the Timing Register before an arbitrary channel is enabled.
Default is 0x30C. A refresh cycle occurs for each 7.8 µs@100 MHz in this
situation.
R/W
R/W
R/W
R/W
R/W
R/W
R/W
⎯
R/W
Figure 9.4.2 SDRAM Timing Register (2/2)
1 _{tCK = Clock cycle}
2 _{tRC is used during (i) refresh cycle time, (ii) single Read, (iii) two transfer burst Reads. The bank cycle time is tRAS +}
t_RP + 1t_CK if t_RAS + t_RP < t_RC in the case of (ii) (iii).
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