TMPR4938 Datasheet, PDF (241/716 Pages) Toshiba Semiconductor – 64-Bit TX System RISC TX49 Family

Chapter 9 SDRAM Controller
9.3.2.3
Address Signal Mapping (32-bit Data Bus)
Table 9.3.3 shows the address signal mapping when using a 32-bit data bus. B0 is used in the
bank selection in memory with a two-bank configuration. [B1:B0] are used in the bank selection
in memory with a four-bank configuration. Bits with the description "L/H" output High when
performing auto-precharging, or output Low when not performing auto-precharging.
Table 9.3.3 Address Signal Mapping (32-bit Data Bus) (1/2)
Row Address Width = 11
Column Address Width = 8
Address Bit
ADDR [19:5]
19 18
(B0) (B1)
17
16
15
(AP)
14
13
12
11
10
9
8
7
6
5
Column
Address
21 22 20 19 L/H L/H L/H 9
8
7
6
5
4
3
2
Row Address
21 22 20 19 20 19 18 17 16 15 14 13 12 11 10
Row Address Width = 11
Column Address Width = 9
Address Bit
ADDR [19:5]
19 18
(B0) (B1)
17
16
15
(AP)
14
13
12
11
10
9
8
7
6
5
Column
Address
22 22 22 22 L/H 22 21 9
8
7
6
5
4
3
2
Row Address
22 22 22 22 20 19 18 17 16 15 14 13 12 11 10
Row Address Width = 11
Column Address Width = 10
Address Bit
ADDR [19:5]
19 18
(B0) (B1)
17
16
15
(AP)
14
13
12
11
10
9
8
7
6
5
Column
Address
23 22 22 23 L/H 22 21 9
8
7
6
5
4
3
2
Row Address
23 22 22 23 20 19 18 17 16 15 14 13 12 11 10
Row Address Width = 12
Column Address Width = 8
Address Bit
ADDR [19:5]
19 18
(B0) (B1)
17
16
15
(AP)
14
13
12
11
10
9
8
7
6
5
Column
Address
22 23 22 21 L/H 23 22 9
8
7
6
5
4
3
2
Row Address
22 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Row Address Width = 12
Column Address Width = 9
Address Bit
ADDR [19:5]
19 18
(B0) (B1)
17
16
15
(AP)
14
13
12
11
10
9
8
7
6
5
Column
Address
23 24 23 21 L/H 23 22 9
8
7
6
5
4
3
2
Row Address
23 24 23 21 20 19 18 17 16 15 14 13 12 11 10
Row Address Width = 12
Column Address Width = 10
Address Bit
ADDR [19:5]
19 18
(B0) (B1)
17
16
15
(AP)
14
13
12
11
10
9
8
7
6
5
Column
Address
24 25 24 21 L/H 23 22 9
8
7
6
5
4
3
2
Row Address
24 25 24 21 20 19 18 17 16 15 14 13 12 11 10
9-7