TMPR4938 Datasheet, PDF (395/716 Pages) Toshiba Semiconductor – 64-Bit TX System RISC TX49 Family

Chapter 11 Serial I/O Port
11.4.3 DMA/Interrupt Status Register 0 (SIDISR0)
DMA/Interrupt Status Register 1 (SIDISR1)
0xF308 (Ch. 0)
0xF408 (Ch. 1)
These registers indicate the DMA or interrupt status information.
31
Reserved
15 14 13 12 11 10
9
8
7
6
5
4
UBRK UVALID UFER UPER UOER ERI TOUT TDIS RDIS STIS Reserved
R
R
R
R
R R/W0C R/W0C R/W0C R/W0C R/W0C
0
1
0
0
0
0
0
1
0
0
RFDN
R
00000
16
: Type
: Initial value
0
: Type
: Initial value
Bit Mnemonic Field Name
31:16
15
UBRK
Reserved
Receive Break
14
UVALID Receive FIFO
Available Status
13
UFER
Frame Error
12
UPER
Parity Error
11
UOER
Overrun Error
10
ERI
Reception Error
Interrupt
9
TOUT
Reception Time
Out
8
TDIS
Transmission
Data Empty
Description
Read/Write
⎯
UART Break (Default: 0)
R
This field indicates the break reception status of the next data in the Receive
FIFO to be read. Reading the Receive FIFO Register (SIRFIFO) updates
the status.
0: No breaks
1: Detect breaks
UART Available Data (Default: 1)
R
This field indicates whether or not data exists in the Receive FIFO
(SIRFIFO).
0: Data exists in the Receive FIFO.
1: No data exists in the Receive FIFO.
UART Frame Error (Default: 0)
R
This field indicates the frame error status of the next data in the Receive
FIFO to be read. Reading the Receive FIFO Register (SIRFIFO) updates
the status.
0: There are no frame errors.
1: There are frame errors.
UART Parity Error (Default: 0)
R
This field indicates the parity error status of the next data in the Receive
FIFO to be read. Reading the Receive FIFO Register (SIRFIFO) updates
the status.
0: There are no parity errors.
1: There are parity errors.
UART Overrun Error (Default: 0)
R
This register indicates the overrun status of the next data in the Receive
FIFO to be read. Reading the Receive FIFO Register (SIRFIFO) updates
the status.
0: There are no overrun errors.
1: There are overrun errors.
Receive Data Error Interrupt (Default: 0)
R/W0C
This bit is immediately set to “1” when a reception error (Frame Error, Parity
Error, or Overrun Error) is detected.
Time Out (Default: 0)
R/W0C
This bit is set to “1” when a reception time out occurs.
Transmit DMA/Interrupt Status (Default: 1)
R/W0C
This bit is set when available space of the amount set by the Transmit FIFO
Request Trigger Level (TDIL) of the FIFO Control Register (SIFCR) exists in
the Transmit FIFO.
Figure 11.4.3 DMA/Interrupt Status Register (1/2)
11-17