TMPR4938 Datasheet, PDF (100/716 Pages) Toshiba Semiconductor – 64-Bit TX System RISC TX49 Family

Chapter 5 Configuration Registers
Bit Mnemonic Field Name
Description
Initial Value Read/Write
25
ACLCKD ACLC Clock Controls clock pulses for the AC-link controller.
Disable
0 = Supply clock pulses.
1 = Do not supply clock pulses.
0
R/W
24
PIOCKD PIO Clock
Controls clock pulses for the parallel IO controller.
0
R/W
Disable
0 = Supply clock pulses.
1 = Do not supply clock pulses.
23 DMA0CKD DMAC0 Clock Controls clock pulses for the DMA controller 0.
Disable
0 = Supply clock pulses.
1 = Do not supply clock pulses.
0
R/W
22
PCICKD PCIC Clock Controls clock pulses for the PCI controller.
Disable
0 = Supply clock pulses.
1 = Do not supply clock pulses.
0
R/W
21
⎯
⎯
Always set this bit to 1.
1
R/W
20
TM0CKD Timer 0 Clock Controls clock pulses for the TMR0 controller.
Disable
0 = Supply clock pulses.
1 = Do not supply clock pulses.
0
R/W
19
TM1CKD Timer 1 Clock Controls clock pulses for the TMR1 controller.
Disable
0 = Supply clock pulses.
1 = Do not supply clock pulses.
0
R/W
18
TM2CKD Timer 2 Clock Controls clock pulses for the TMR2 controller.
Disable
0 = Supply clock pulses.
1 = Do not supply clock pulses.
0
R/W
17
SIO0CKD SIO0 Clock
Controls clock pulses for the SIO0 controller.
Disable
0 = Supply clock pulses.
1 = Do not supply clock pulses.
0
R/W
16
SIO1CKD SIO1 Clock
Controls clock pulses for the SIO1 controller.
Disable
0 = Supply clock pulses.
1 = Do not supply clock pulses.
0
R/W
15 ETHC1RST ETHERC1
Reset
Resets the ETHER controller 1.
0 = Normal state
1 = Reset
0
R/W
14 ETHC0RST ETHERC0
Reset
Resets the ETHER controller 0.
0 = Normal state
1 = Reset
0
R/W
13
SPIRST SPI Reset
Resets the SPI controller.
0
R/W
0 = Normal state
1 = Reset
12 SRAMRST SRAMC Reset Resets the internal SRAM controller.
0
R/W
0 = Normal state
1 = Reset
11 PCIC1RST PCIC1 Reset Resets the PCI controller 1.
1
R/W
0 = Normal state
1 = Reset
10 DMA1RST DMAC1 Reset Resets the DMAC controller 1.
0
R/W
0 = Normal state
1 = Reset
9
ACLRST ACLC Reset Resets the AC-link controller.
0
R/W
0 = Normal state
1 = Reset
Note: Reset the AC-link controller when it is not asserting the
interrupt and DMA request.
8
PIORST PIO Reset
Resets the parallel IO controller.
0
R/W
0 = Normal state
1 = Reset
Figure 5.2.5 Clock Control Register (2/3)
5-12