TMP19A71CYFG Datasheet, PDF (51/402 Pages) Toshiba Semiconductor – 32-Bit RISC Microprocessor

TMP19A71
7.8.3
Detection of Interrupt Requests
An interrupt request detection varies by a source as shown in Table 7.8.3. All interrupt
requests, after being detected, are sent to the INTC for priority arbitration and then sent
to the TX19A core processor, as illustrated in Figure 7.8.1. For a detection level that can be
used by each interrupt source, refer to Table 7.8.5.
Interrupt Type
(1) External pin interrupt
INT0 to INT3
(2) External pin interrupt
INT4 to INT9
(3) Emergency stop interrupt
INTEMGx
(4) Emergency stop interrupt
INTTBE0
(5) Other interrupts
Table 7.8.3 Detecting Part of Interrupt Request
Detecting Part
CG
Interrupt Notification Route
PortT → CG (detection) → INTC (arbitration) → TX19A core
INTC
Port → INTC (detection/arbitration) → TX19A core
Port
Pprt (detection) → PMD → INTC (arbitration) → TX19A core
Port
Port (detection) →INTC (arbitration) → TX19A core
INTC
Peripheral hardware →INTC (detection/arbitration) → TX19A core
TX19A
Core
CG
External Pin Interrupt
INT0 to INT3
INTEMGx
PMD
EMG
IRC
Detection
Emergency stop interrupt
Circuit
INTEMGx/INTTBE0
(Port)
INTTBE0
Other interrupt
Figure 7.8.1 Notification Route of Interrupt
TMP19A71 7-10