TMP19A71CYFG Datasheet, PDF (43/402 Pages) Toshiba Semiconductor – 32-Bit RISC Microprocessor

TMP19A71
7.2 Exception Vectors
An exception vector address is the entry address of a routine that handles an exeption. Reset
and Nonmaksable Interrupt exceptions are vectored to address 0xBFC0_0000. A debug
exception is vectored to 0xBFC0_0480 when the EJTAG ProbEn signal is 0 and 0xFF20_0200
when the EJTAG ProbEn signal is 1 according to the internal signal value of ProbEn.Values of
other exceptions may be various depending on the BEV bit of the Status register and the IV bit
of the Cause register belonging to the system control coprocessor (CP0).
Table 7.2.1 Exception Vector Table (Virtual Addresses)
Exception Type
Reset, NMI
Debug exception (En=0)
Debug exception (En=1)
Interrupt (IV=0)
Interrupt (IV=1)
Other general exceptions
BEV=0
0xBFC0_0000
0xBFC0_0480
0xFF20_0200
0x8000_0180
0x8000_0200
0x8000_0180
BEV=1
0xBFC0_0000
0xBFC0_0480
0xFF20_0200
0xBFC0_0380
0xBFC0_0400
0xBFC0_0380
Note 1 : When exception vector addresses reside in the on-chip ROM, the BEV bit of the CP0 Status register must
be set to 1. TMP19A71 has no external bus interface, so Status.BEV=0 is not allowed.
Note 2 : To assign different exception vector addresses for interrupts and other general exceptions, set the IV bit
of the CP0 Cause register to 1.
7.3 Reset Exception
A Reset exception occurs when an external reset pin is driven low or the WDT counts to its
reset value. As a Reset exception occurs, on-chip peripheral registers (Note 1) and CP0
registers are initialied, and a control jumps to the exception vector address 0xBFC0_0000.
Upon a Reset exception, the PC value is stored in the CP0 ErrorEPC register.
When a Reset exception occurs, the ERL bit of the CP0 Status register is set to 1, disabling
interrupts. To use interrupts, the ERL bit must be cleared to 0 in the startup routine (reset
exception handler) or by other means.
For a detailed description of Reset exception handling, refer to the chapter Exception
Handling Reset Exception in the 32-Bit TX19 System RISC TX19 Family Architecture manual.
Note 1 : In the flash-version product, some on-chip peripheral registers are not initialized by a Reset exception;
these registers are initialized only by the internal power-on reset signal that is generated at power-on.
Note 2 : In the mask-version product, some on-chip registers are not initialized by a Reset exception caused by
the WDT; these registers are initialized only by a Reset exception via an external reset pin.
TMP19A71 7-2