TMP19A71CYFG Datasheet, PDF (363/402 Pages) Toshiba Semiconductor – 32-Bit RISC Microprocessor

TMP19A71
12) Flash Control/Status Register
This is a 32-bit register for monitoring the status of the flash memory.
In Programmer mode, the RDY/BSY output is provided for the host system to monitor
the status of an embedded algorithm. The TX19A core processor can poll the RDY/BSY
bit in the FLCS register for the same purpose. The RDY/BSY bit is cleared to 0 when
the flash memory is performing an embedded operation. The RDY/BSY bit is set to 1
when an embedded operation has completed and the flash memory is ready to accept
the next command. If any failure occurs during an embedded operation, this bit
remains 0. A hardware reset sets this bit to 1.
The RDY/BSY bit is cleared to 0 upon completion of the final bus write cycle of an
embedded operation command, with one exception. In the case of the Auto Block Erase
command, this bit is cleared after the time-out has expired. Any command is ignored
while the RDY/BSY bit is cleared.
FLCS
(0xFFFF_E520)
7
6
5
4
3
2
1
0
Bit Symbol
―
―
Read/Write
W
R
Reset Value
0
0
Function
Must be set
to 0.
―
―
MROM
RDY/BSY
―
―
R
R/W
R
R
W
R
0
0
0
1
0
0
Must be set 0:Flash
Ready/Busy Must be set
to 0.
1:Mask
0: Busy
to 0.
1: Ready
15
14
13
12
11
10
9
8
Bit Symbol
―
―
―
―
―
―
―
―
Read/Write
R
R
R
R
R
R
R
R
Reset Value
0
0
0
0
0
0
0
0
23
22
21
20
19
18
17
16
Bit Symbol
―
―
―
―
―
―
―
―
Read/Write
R
R
R
R
R
R
R
R
Reset Value
0
0
0
0
0
0
0
0
31
30
29
28
27
26
25
24
Bit Symbol
―
―
―
―
―
―
―
―
Read/Write
W
R
R
R
R
R
R
R
Reset Value
―
0
0
0
0
0
0
0
Note 1:
Note 2:
Note 3:
This register must be accessed as a 32-bit quantity.
This register does not support bit manipulation instructions.
In the mask-version device, the MROM bit is set to 1 and any other bits are read-only with the same
initial values.
TMP19A71 17-59