TMP19A71CYFG Datasheet, PDF (145/402 Pages) Toshiba Semiconductor – 32-Bit RISC Microprocessor

TMP19A71
10.2.4 Register Description
The DMAC has fifty 32-bit registers, as listed in Table 10.2.1 .
Table 10.2.1 DMAC Register Map (1/2)
Address
0xFFFF_D600
0xFFFF_D604
0xFFFF_D608
0xFFFF_D60C
0xFFFF_D610
0xFFFF_D618
0xFFFF_D620
0xFFFF_D624
0xFFFF_D628
0xFFFF_D62C
0xFFFF_D630
0xFFFF_D638
0xFFFF_D640
0xFFFF_D644
0xFFFF_D648
0xFFFF_D64C
0xFFFF_D650
0xFFFF_D658
0xFFFF_D660
0xFFFF_D664
0xFFFF_D668
0xFFFF_D66C
0xFFFF_D670
0xFFFF_D678
0xFFFF_D680
0xFFFF_D684
0xFFFF_D688
0xFFFF_D68C
0xFFFF_D690
0xFFFF_D698
0xFFFF_D6A0
0xFFFF_D6A4
0xFFFF_D6A8
0xFFFF_D6AC
0xFFFF_D6B0
0xFFFF_D6B8
0xFFFF_D6C0
0xFFFF_D6C4
0xFFFF_D6C8
0xFFFF_D6CC
0xFFFF_D6D0
0xFFFF_D6D8
Symbol
CCR0
CSR0
SAR0
DAR0
BCR0
DTCR0
CCR1
CSR1
SAR1
DAR1
BCR1
DTCR1
CCR2
CSR2
SAR2
DAR2
BCR2
DTCR2
CCR3
CSR3
SAR3
DAR3
BCR3
DTCR3
CCR4
CSR4
SAR4
DAR4
BCR4
DTCR4
CCR5
CSR5
SAR5
DAR5
BCR5
DTCR5
CCR6
CSR6
SAR6
DAR6
BCR6
DTCR6
Register Name
Channel Control Register (Channel 0)
Channel Status Register (Channel 0)
Source Address Register (Channel 0)
Destination Address Register (Channel 0)
Byte Count Register (Channel 0)
DMA Transfer Control Register (Channel 0)
Channel Control Register (Channel 1)
Channel Status Register (Channel 1)
Source Address Register (Channel 1)
Destination Address Register (Channel 1)
Byte Count Register (Channel 1)
DMA Transfer Control Register (Channel 1)
Channel Control Register (Channel 2)
Channel Status Register (Channel 2)
Source Address Register (Channel 2)
Destination Address Register (Channel 2)
Byte Count Register (Channel 2)
DMA Transfer Control Register (Channel 2)
Channel Control Register (Channel 3)
Channel Status Register (Channel 3)
Source Address Register (Channel 3)
Destination Address Register (Channel 3)
Byte Count Register (Channel 3)
DMA Transfer Control Register (Channel 3)
Channel Control Register (Channel 4)
Channel Status Register (Channel 4)
Source Address Register (Channel 4)
Destination Address Register (Channel 4)
Byte Count Register (Channel 4)
DMA Transfer Control Register (Channel 4)
Channel Control Register (Channel 5)
Channel Status Register (Channel 5)
Source Address Register (Channel 5)
Destination Address Register (Channel 5)
Byte Count Register (Channel 5)
DMA Transfer Control Register (Channel 5)
Channel Control Register (Channel 6)
Channel Status Register (Channel 6)
Source Address Register (Channel 6)
Destination Address Register (Channel 6)
Byte Count Register (Channel 6)
DMA Transfer Control Register (Channel 6)
TMP19A71 10-4