TMP19A71CYFG Datasheet, PDF (41/402 Pages) Toshiba Semiconductor – 32-Bit RISC Microprocessor

TMP19A71
6.2.2
Watchdog Timer Control Register (WDCR)
This register is used to disable the WDT and to clear the WDT binary counter.
Watchdog Timer Control Register
7
6
5
4
3
2
1
0
WDCR
Bit Symbol
―
（0xFFFF_C834） Read/Write
W
Reset Value
⎯
Function
B1H : WDT disable code
4E H: WDT clear-count code
WDT disable and clear -count
0xB1 Disable code
0x4E Clear-count code
Others Invalid
Note: This register does not support bit manipulation instructions.
• Disabling the WDT
The WDT can be disabled by clearing the WDMOD.WDEN to 0 and then writing the
disable code (B1H) to the WDCR register. At this time, the counter value is
maintained. Before enabling the WDT again, clear the counter by writing the
clear-count code (4EH).
WDMODL ← − − − − − 0 − −
WDCR
←1 0 1 1 0 0 0 1
Clear the WDEN bit to 0.
Write the disable code (B1H) to the WDCR.
• Enabling the WDT
The WDT can be enabled simply by setting the WDEN bit in the WDMOD to 1.
• Clearing the WDT counter
Writing the clear-count code (4EH) to the WDCR resets the binary counter to 0. The
counting process begins again.
WDCR
←0 1 0 0 1 1 1 0
Write the clear-count code (4EH) to the WDCR.
Watchdog Counter Register
7
6
5
4
3
2
1
0
Bit Symbol
―
WDCNT
（0xFFFF_C838） ^Read/Write
R
Reset Value
0
Function
15
14
13
12
11
10
9
8
Bit Symbol
―
Read/Write
R
Reset Value
0
Function
Bits 22 to 7 of the WDT counter value can be read.
TMP19A71 6-4