TMP19A71CYFG Datasheet, PDF (187/402 Pages) Toshiba Semiconductor – 32-Bit RISC Microprocessor

TMP19A71
11.4.5 One-Shot Pulse Generation Using an External Trigger Pulse
The TMRBn can be used to produce a one-time pulse as follows.
(1) The 16-bit up-counter (TB0CNT) is programmed to function as a free-running
counter, clocked by one of the prescaler outputs. The TB0IN pin is used as an
active-high external trigger pulse input for latching the counter value into the
capture register (TB0CP0).
(2) The Interrupt Controller (INTC) must be programmed to generate an
INTTBCAP01 interrupt upon detection of a rising edge on the TB0IN pin. The
TB0REG0 is loaded with the sum of the TB0CP0 value (c) and the pulse delay
(d)―i.e., (c) + (d). The TB0REG1 is loaded with the sum of the TB0REG0 value
and the pulse width (p)―i.e., (c) + (d) + (p).
(3) Next, the INVC0 and INVC1 bits in the timer flip-flop control register (TB0FF)
are set to 11, so that the timer flip-flop (TB0FF) will toggle when a match is
detected between the TB0CNT and the TB0REG0 and between the TB0CNT and
the TB0REG1. With the TB0FF toggled twice, a one-shop pulse is produced.
Upon a match between the TB0CNT and the TB0REG1, the TMRB0 generates
the INTTBCOM01 interrupt, which must disable the toggle trigger for the
TB0FF.
Figure 11.4.6 depicts one-shot pulse generation, with annotations showing (c), (d)
and (p).
Counter Clock
(Internal Clock)
TB0IN0 Input Pin
(External Trigger Pulse)
TB0REG0 Match
TB0REG1 Match
TB0OUT (Timer Output) Pin
The counter is free-running.
c
c+d
c+d+p
The TB0CNT value is latched into TB0CP0.
INTTBCAP01 is generated.
INTTBCOM00 is
generated.
Toggle is
enabled.
Toggle is disabled
for a capture into
TB0CP1.
Delay
(d)
Toggle is
enabled.
INTTBCOM01
is generated.
Pulse Width
(p)
Figure 11.4.6 One-Shop Pulse Generation (with a Delay)
TMP19A71 11-17