TMP19A71CYFG Datasheet, PDF (47/402 Pages) Toshiba Semiconductor – 32-Bit RISC Microprocessor

TMP19A71
Set Cause.IP[1:0] to 1 to generate an interrupt
Automatically jump to the exception vector address
Read Cause.IP[1:0] to determine the cause of the interrupt
Clear Cause.IP[1:0] to 0 to clear the interrupt
Jump to the interrupt handler
Save relevant registers on the stack
Interrupt handler routine
Handled by user software
Handled by TX19A core
Handled by user software
Restore the saved registers from the stack
ERET instruction
Return to the address where the interrupt occurred
Figure 7.7.1 Example of Softwre Interrupt Operation
Note: A software interrupt is accepted, at the fastest, 3 clock cycles after the interrupt is enabled, and the PC at
this moment is stored in the EPC register.
TMP19A71 7-6