TMP19A71CYFG Datasheet, PDF (294/402 Pages) Toshiba Semiconductor – 32-Bit RISC Microprocessor

TMP19A71
Table 15.2.1 Detailed Description of the Encoder Input Control Register
Name
Encoder pulse counter clear
Encoder rotation direction
Z phase detection state
Counter clear by phase Z
Encoder pulse counter enable
Noise filter
Encoder interrupt request
Symbol
ENCLR
U/D
ZDET
ZEN
CUNEN
NR1,0
ENCAP
Function
Writing a 1 and then a 0 to this bit clears the encoder counter to 0. Then, the counter
starts counting again.
When the motor is rotating in CW direction (phase A of the incremental encoder
signal is 90 degrees ahead of phase B), this bit is set to 1. When the motor is rotating
in CCW direction (phase A is 90 degrees behind phase B), this bit is cleared to 0.
This bit is cleared to 0 when a 1 is written to the CUNEN bit and at reset. It is set to 1
on the next ZDETECT—the signal to be output on the rising edge (CW direction) or
falling edge (CCW direction) of the incremental encoder signal phase Z. (This bit is
independent of the ZEN value.)
When the motor is rotating in CW direction, this bit is cleared to 0 on the rising edge
of phase Z (ZDETECT). When the motor is rotating in CCW direction, this bit is
cleared to 0 on the falling edge of phase Z (ZDETECT). If ENCLK (a clock obtained
by multiplying the phase A and phase B signals by 4) and ZDETECT coincide with
each other, the counter is cleared to 0 without counting.
When CUNEN=1, the ZDET bit is cleared to 0 and the encoder counter (ENCNT) is
enabled. When CUNEN=0, the encoder counter is disabled.
00: No filter
01: Eliminate pulses of less than 31/IMCLK as noise (1.11 μs IMCLK = 28 MHz)
10: Eliminate pulses of less than 63/IMCLK as noise (2.25 μs IMCLK = 28 MHz)
11: Eliminate pulses of less than 127/IMCLK as noise (4.54 μs IMCLK = 28 MHz)
ENCAP=1 enables interrupt request signal generation. ENCAP=0 disables interrupt
request signal generation.
TMP19A71 15-3