TH50VSF3680 Datasheet, PDF (48/55 Pages) Toshiba Semiconductor – SRAM AND FLASH MEMORY MIXED MULTI-CHIP PACKAGE

TH50VSF3680/3681AASB
TIMING FOR SWITCHING BETWEEN FLASH AND SRAM MODES
CEF
CE1S
t_CCR
t_CCR
CE2S
Notes:
(1)
(2)
(3)
(4)
(5)
(6)
WE remains High during a Read cycle.
If CE1S goes Low (or CE2S goes High) at the same time as or after WE goes Low, the outputs will
remain High-Impedance.
If CE1S goes High (or CE2S goes Low) at the same time as or before WE goes High, the outputs will
remain High-Impedance.
If OE is High during a Write cycle, the outputs will remain High-Impedance.
Because I/O pins may be in Output state at this point, input signals of the opposite value must not be
applied.
DOUT6 stops toggling when the last command has been completed.
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