TH50VSF3680 Datasheet, PDF (21/55 Pages) Toshiba Semiconductor – SRAM AND FLASH MEMORY MIXED MULTI-CHIP PACKAGE

TH50VSF3680/3681AASB
AC CHARACTERISTICS (SRAM) (Ta = −20°~85°C, V_CCs = 2.7 V~3.3 V)
Read cycle
SYMBOL
PARAMETER
MIN
t_RC
Read Cycle Time
90
t_ACC
Address Access Time

t_CO1
Chip Enable ( CE1S ) Access Time

t_CO2
Chip Enable (CE2S) Access Time

t_OE
Output Enable Access Time

t_BA
Data Byte Control Access Time

t_COE
Chip Enable Low to Output Active
5
t_OEE
Output Enable Low to Output Active
0
t_BE
Data Byte Control Low to Output Active
0
t_OD
Chip Enable High to Output Hi-Z

t_ODO
Output Enable High to Output Hi-Z

t_BD
Data Byte Control High to Output Hi-Z

t_OH
Output Data Hold Time
10
t_CCR
CE Recovery Time
0
MAX

90
90
90
45
45



30
30
30


UNIT
ns
Write cycle
SYMBOL
PARAMETER
t_WC
t_WP
t_CW
t_BW
t_AS
t_WR
t_ODW
t_OEW
t_DS
t_DH
Write Cycle Time
Write Pulse Width
Chip Enable to End of Write
Data Byte Control to End of Write
Address Set-up Time
Write Recovery Time
WE Low to Output Hi-Z
WE High to Output Active
Data Set-up Time
Data Hold Time
MIN
MAX
UNIT
70

50

60

50

0

ns
0


30
0

30

0

AC TEST CONDITIONS
PARAMETER
Input Pulse Level
Input Pulse Rise and Fall Time (10%~90%)
Timing Measurement Reference Level (input)
Timing Measurement Reference Level (output)
Output Load
VALUES
0.4 V, 2.4 V
5 ns
V_CCs × 0.5
V_CCs × 0.5
C_L (100 pF) + 1 TTL gate
2001-03-06 21/55