TH50VSF3680 Datasheet, PDF (23/55 Pages) Toshiba Semiconductor – SRAM AND FLASH MEMORY MIXED MULTI-CHIP PACKAGE

COMMAND WRITE/PROGRAM/ERASE CYCLE
SYMBOL
PARAMETER
t_CMD
t_AS
t_AH
t_AHW
t_DS
t_DH
t_WELH
t_WEHH
t_CES
t_CEH
t_CELH
t_CEHH
t_WES
t_WEH
t_OES
t_OEHP
t_OEHT
t_BEH
t_VCS
t_BUSY
t_RP
t_READY
t_RB
t_RH
t_CEBTS
t_SUSP
t_RESP
t_SUSE
t_RESE
Command Write Cycle Time
Address Set-up Time / CIOF Set-up Time
Address Hold Time / CIOF Hold Time
Address Hold Time from WE High level
Data Set-up Time
Data Hold Time
WE Low-Level Hold Time
WE High-Level Hold Time
CEF Set-up Time to WE Active
CEF Hold Time from WE High Level
CEF Low-Level Hold Time
CEF High-Level Hold Time
WE Set-up time to CEF Active
WE Hold Time from High Level
OE Set-up Time
OE Hold Time (Toggle/Data Polling)
OE High-Level Hold Time (Toggle)
Erase Hold Time
V_CCf Set-up Time
Program/Erase-Valid-to- RY/BY Delay
RESET Low-Level Hold Time
RESET Low-Level to Read Mode
RY/BY Recovery Time
RESET Recovery Time
CEF Set-up time (CIOF control)
Program Suspend Command to Suspend Mode
Program Resume Command to Program Mode
Erase Suspend Command to Suspend Mode
Erase Resume Command to Erase Mode
TH50VSF3680/3681AASB
( WE Control)
( WE Control)
( WE Control)
( WE Control)
( CEF Control)
( CEF Control)
( CEF Control)
( CEF Control)
MIN
MAX
UNIT
100

ns
0

ns
50

ns
20

ns
50

ns
0

ns
50

ns
20

ns
0

ns
0

ns
50

ns
20

ns
0

ns
0

ns
0

ns
90

ns
20

ns
50

µs
500

µs

90
ns
500

ns

20
µs
0

ns
50

ns
5

ns

1.5
µs

1
µs

15
µs

1
µs
2001-03-06 23/55