TH50VSF3680 Datasheet, PDF (20/55 Pages) Toshiba Semiconductor – SRAM AND FLASH MEMORY MIXED MULTI-CHIP PACKAGE

TH50VSF3680/3681AASB
DC CHARACTERISTICS (Ta = −20°~85°C, V_CCs/V_CCf = 2.7 V~3.3 V)
SYMBOL
PARAMETER
CONDITION
MIN TYP. MAX UNIT
I_IL
Input Leakage Current
Input Leakage Current
I_ILW
( WP/ACC pin)
V_IN = 0 V~V_CC
0 V ≤ V_IN ≤ V_CC
  ±1 µA
  ±10 µA
I_SOH
I_SOL
I_FOH1
I_FOH2
I_FOL
I_LO
I_CCO1
I_CCO2
SRAM Output High Current
V_OH = V_CCs − 0.5 V
SRAM Output Low Current
V_OL = 0.4 V
Flash Output High Current (TTL) V_OH = 2.4 V
Flash Output High Current
(CMOS)
V_OH = V_CCf × 0.85
V_OH = V_CCf − 0.4 V
Flash Output Low Current
V_OL = 0.4 V
Output Leakage Current
V_OUT = 0 V~V_CC, OE = V_IH
Flash Average Read Current
CEF = V_IL, OE = V_IH, I_OUT = 0 mA,
t_cycle = t_RC(min)
Flash Average Program/
Erase Current
CEF = V_IL, OE = V_IH, I_OUT = 0 mA
−0.5 
2.1 
−0.4 
−2.5 
−100 
4

 mA
 mA
 mA
 mA
 µA
 mA
±1 µA
  30 mA
  15 mA
I_CCO3
I_CCO4
SRAM Average Operating
Current
CE1S = V_IL, CE2S = V_IH,
OE = V_IH, I_OUT = 0 mA
t_cycle = t_RC
  50
mA
t_cycle = 1 MHz   10
CE1S = 0.2 V, OE = V_CCs − 0.2 V, ^{tcycle = tRC}
CE2S = V_CCs − 0.2 V, I_OUT = 0 mA _{tcycle = 1 MHz}




45
mA
5
I_CCO5
Flash Average
Read-While-Program Current
V_IN = V_IH/V_IL, I_OUT = 0 mA, t_cycle = t_RC(min)
  45 mA
I_CCO6
Flash Average
Read-While- Erase Current
V_IN = V_IH/V_IL, I_OUT = 0 mA, t_cycle = t_RC(min)
  45 mA
I_CCO7
Flash Average Program-While-
Erase-Suspend Current
V_IN = V_IH/V_IL, I_OUT = 0 mA
  15 mA
I_CCS1
I_CCS2
Flash Standby Current
Flash Standby Current
(Automatic Sleep Mode⁽¹⁾)
CEF = RESET = V_CCf or RESET = V_SS
V_IH = V_CCf or V_IL = V_SS
  10 µA
  10 µA
I_CCS3
I_CCS4
SRAM Standby Current
CE1S = V_IH or CE2S = V_IL
  2 mA
Ta = 25°C
 1
V_CCs = 3.3 V
Ta = −20~85°C   10
o^Cr^EC¹E^S2S^==V0C.2^CsV^{−(20) .2 V}
Ta = 25°C
 0.01 0.5 µA
V_CCs = 3.0 V Ta = −20~40°C   1
Ta = −20~85°C   5
I_ACC
High Voltage Input Current for
WP/ACC
8.5 V ≤ V_ACC ≤ 9.5 V
  20 mA
(1) The device is going to Automatic Sleep Mode, when address remain steady during 150 ns.
(2) In Standby Mode, with CE1S ≥ V_CCs − 0.2 V, these limits are guaranteed when CE2S ≥ V_CCs − 0.2 V or CE2S ≤ 0.2 V and
CIOS ≥ V_CCs − 0.2 V or CIOS ≤ 0.2 V.
2001-03-06 20/55