TC9446FG Datasheet, PDF (23/41 Pages) Toshiba Semiconductor – Audio Digital Processor for Decode of Dolby Digital (AC-3), MPEG2 Audio

TC9446FG
3) DIR input part
When you input a signal into DIR, please be sure to input, as shown in Figure 17 through a signal
amplification circuit, a 5 V-3 V conversion circuit, etc.
COAXIAL
V_SS
5V
OPTICAL
V_SS
3V
V_SS
5 V-3 V level shifter
34
RX
DIR
(3 V input)
Figure 17 DIR Input Part
4) Lock detection
When VCO circuit locks LOCK terminal and it is operating, “H” level is outputted and “L” level is
outputted at the time of the Ann lock. At the time of the Ann lock, latch operation of reception
recovery data and channel status is stopped, and it holds last value. If the state of a no error
continues the time of the following table, LOCK terminal will be set to “H” level and a reception
recovery will be started.
Period of error
t_A
LOCK Terminal
Data of Receiving
Demodulation
Channel Status
t_B
Figure 18 Internal Operation Timing at Time of Error
Table 3 Release Time After the Lock Detection Operation
Sampling Frequency (kHz)
32
44.1
48
96
Data of Receiving Demodulation t_A (ms)
384.0
278.6
256.0
128.0
Channel Status t_B (ms)
288.0
209.0
192.0
96.0
23
2005-09-28