TC9446FG Datasheet, PDF (22/41 Pages) Toshiba Semiconductor – Audio Digital Processor for Decode of Dolby Digital (AC-3), MPEG2 Audio

TC9446FG
4. Read/Write of Command
Write and a read of command change with decode programs built in.
For details, please refer to program explanation data.
5. Digital Audio Interface (DIR/DIT)
1) A setup of DIR/DIT
The digital reception recovery (DIR) for the audio interfaces and the abnormal-conditions
transmission (DIT) based on CEI “IEC958 standard” and the JEITA “CP-1201 standard” are built in.
DIR corresponds to the input of 96 kHz sampling (2 channels). Please refer to program explanation
data about the various contents of a setting of DIR/DIT.
2) VCO oscillation and PLL
Since VCO oscillation circuit is built in, PLL circuit can consist of connecting an external low path
filter simply. VCO oscillation circuit and the example of composition of PLL are shown in Figure 16.
(A) Crystal/XI clock
Setting of command register
Timing
generator
Selector
VCO circuit
48
LOCK
47
CKO
46
V_SSA
45
CKI
44
AMPO
Clock output
V_DDA
V_SSA
External clock input
(when CKI does not use, it
connect to V_SS line.)
V_DD/2
43
AMPI
Phase detector
Frequency
detector
Demodulation
circuit
42
PLON
41
V_DDA
40
PDO
37
FCONT
34
RX
Modulation circuit
31
TXO
L: CKI/XI clock
H: VCO clock
V_SS
DIR input ^VSSA
DIT output
Figure 16 VCO Oscillation Circuit and Example of Composition of PLL
22
2005-09-28