TC9446FG Datasheet, PDF (19/41 Pages) Toshiba Semiconductor – Audio Digital Processor for Decode of Dolby Digital (AC-3), MPEG2 Audio

TC9446FG
3) Read of 24 bit data
The number of words of data read while data required for the 16 bit address in a 24 bit command is
set up and R/W bit is set to “L”, when reading data of TC9446FG from a MCU during program
operation is set up.
And, after transmitting a 24 bit command, I²C Address is set to 3Bh after the term progress for
about 6 ms, and it transmits with START Condition. Then, 24 bit data of the required number of
words is read.
Although ACK bit of a data Read term needs to give “L” from a MCU, it needs to set only ACK bit
added to last 8 bit data to “H”.
This is because the Basra in of SDA where TC9446FG are the master is opened wide and a MCU
can transmit STOP Condition.
In addition, the term progress for about 6 ms after command transmission is for waiting to set data
which should be read to data buffer of TC9446FG.
The procedure of read-out of 24 bit data is shown in Figure 13.
START Condition
Transmission of I²C Address (3Ah)
At the time of ACK = “H”, it resumes from
START Condition.
Checking of ACK bit = “L”
Transmission of 24 bit command
(read of data = xxxx1xh)
A term is stood by for about 6 ms.
A 16 bit address and a transmission word
number are set up.
START Condition
Transmission of I²C Address (3Bh)
At the time of ACK = “H”, it resumes from
START Condition.
Checking of ACK bit = “L”
Read of 24 bit data (1)
Read of 24 bit data (2)
It is possible to Write in the 24 bit data
until 16 word maximum.
Read of 24 bit data (n)
The last ACK bit is set to “H”.
STOP Condition
It finished to read of the data
Figure 13 Procedure of Read-Out of 24 Bit Data
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2005-09-28