TC9446FG Datasheet, PDF (16/41 Pages) Toshiba Semiconductor – Audio Digital Processor for Decode of Dolby Digital (AC-3), MPEG2 Audio

TC9446FG
2-2-2. The Data Transmission Method in I²C Mode
1) Program boot and a program start
As for TC9446FG, RAM is assigned 128 words of program address 0000h-007Fh, and the
interruption vector address is become 0000h-0009h.
Therefore, in order to operate TC9446FG, it needs to interrupt at least and a program needs to be
booted to a vector address.
In addition, a program load needs to be continuously performed to an interruption vector address to
store a program in 000Ah-007Fh.
In order to perform program boot, the program RAM boot start bit and the soft reset bit in the 24
bit command transmitted after reset need to be set to “H”. (command = 000060h)
And after command transmission, program data (40 bits) is divided into 20 bits of a higher rank/low
rank, and it transmits by the low-rank stuffing of 24 bit data in the order of a higher rank (20 bits)
and a low rank (20 bits).
Since a write-in address is made automatic (+1) from 0000h, if it transmits the required number of
words and END Condition is transmitted, program boot will complete it.
In addition, the write-in address of program boot always starts from 0000h.
A start of a program is performed by carrying out and transmitting the soft reset bit in a 24 bit
command to “L”, and transmitting END Condition, without performing data transmission.
The procedure of program boot and a program start is shown in Figure 11.
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2005-09-28