DAC38RF86 Datasheet, PDF (99/141 Pages) Texas Instruments – Dual- or Single-Channel, Single-Ended, 14-bit, 9-GSPS, RF-Sampling DAC with JESD204B Interface and On-Chip GSM PLL

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8.5.55 JESD ILA Check 2 Register (address = 0x54) [reset = 0x8E60]
DAC38RF86, DAC38RF87
DAC38RF97, DAC38RF96
SLASEF4 – FEBRUARY 2017
Figure 106. JESD ILA Check 2 Register (JESD_ILA_CFG2)
15
14
13
12
11
10
9
8
0
0
0
0
0
0
0
x
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
7
6
5
4
3
2
1
0
0
1
0
1
0
1
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 96. JESD_ILA_CFG2 Field Descriptions
Bit Field
15
ILA_HD
14:10 ILA_L
9:5 ILA_K
4:0 ILA_S
Type
R/W
R/W
R/W
R/W
Reset
1
00011
10011
00000
Description
JESD HD configuration value used only for ILA checking; may
be set independently of the actual JESD mode
JESD L-1 configuration value used only for ILA checking; may
be set independently of the actual JESD mode
JESD K-1 configuration value used only for ILA checking; may
be set independently of the actual JESD mode
JESD S-1 configuration value used only for ILA checking; may
be set independently of the actual JESD mode
8.5.56 JESD SYSREF Mode Register (address = 0x5C) [reset = 0x0001]
Figure 107. JESD SYSREF Mode Register (JESD_SYSR_MODE)
15
14
13
12
11
10
9
8
0
0
0
0
0
0
0
x
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
7
6
5
4
3
2
1
0
0
1
0
1
1
1
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Bit Field
15:4 Reserved
3
ERR_CNT_CLR
2:0 SYSREF_MODE
Table 97. JESD_SYSR_MODE Field Descriptions
Type
R/W
R/W
Reset
0x000
0
R/W
001
Description
Reserved
A transition from 0->1 causes the error_cnt to be cleared
Determines how SYSREF is used in the JESD synchronizing
block.
000 = Don’t use SYSREF pulse
001 = Use all SYSREF pulses
010 = Use only the next SYSREF pulse
011 = Skip one SYSREF pulse then use only the next one
100 = Skip one SYSREF pulse then use all pulses.
101 = skip two SYSREFs and then use one
110 = skip two SYSREFs and then use all
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