DAC38RF86 Datasheet, PDF (124/141 Pages) Texas Instruments – Dual- or Single-Channel, Single-Ended, 14-bit, 9-GSPS, RF-Sampling DAC with JESD204B Interface and On-Chip GSM PLL

DAC38RF86, DAC38RF87
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SLASEF4 – FEBRUARY 2017
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8.5.88 Serdes Polarity Control Register (address = 0x3F) [reset = 0x0000]
Figure 139. Serdes Polarity Control Register (SRDS_POL)
15
14
13
12
11
10
9
8
0
0
0
0
0
0
0
x
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
7
6
5
4
3
2
1
0
0
0
1
1
1
1
1
1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 129. SRDS_POL Field Descriptions
Bit Field
15:8 Reserved
7:0 INVPAIR
Type
R/W
Reset
0x00
R/W
0x00
Description
Reserved
Allows the PN pairs of the different lanes to be inverted.
bit 7 = lane7
bit 6 = lane6
bit 5 = lane5
bit 4 = lane4
bit 3 = lane3
bit 2 = lane2
bit 1 = lane1
bit 0 = lane0
8.5.89 JESD204B SYNCB OUTPUT Register (address = 0x76) [reset = 0x0000]
Figure 140. JESD204B SYNCB OUTPUT Register (SYNCBOUT)
15
14
13
12
11
10
9
8
0
0
0
0
0
0
0
x
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
7
6
5
4
3
2
1
0
0
0
1
1
1
0
1
1
R/W
R/W
R/1W
R/W
R/W
R/W
R/W
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after rese1t
Bit Field
15:2 Reserved
1
SYNCBOUT1
0
SYNCBOUT0
Table 130. SYNCBOUT Field Descriptions
Type
R/W
R/W
R/W
Reset
0x00
0
0
Description
Reserved
If the CMOS SYNC outputs are turned on, this bit will show the
status of the JESD SYNCB1 signal
If the CMOS SYNC outputs are turned on, this bit will show the
status of the JESD SYNCB0 signal
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