DAC38RF86 Datasheet, PDF (121/141 Pages) Texas Instruments – Dual- or Single-Channel, Single-Ended, 14-bit, 9-GSPS, RF-Sampling DAC with JESD204B Interface and On-Chip GSM PLL

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DAC38RF86, DAC38RF87
DAC38RF97, DAC38RF96
SLASEF4 – FEBRUARY 2017
8.5.84 Serdes Clock Configuration Register (address = 0x3B) [reset = 0x0002]
Figure 135. Serdes Clock Configuration Register (SRDS_CLK_CFG)
15
14
13
12
11
10
9
8
0
0
0
0
0
0
0
x
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
7
6
5
4
3
2
1
0
0
0
1
1
1
0
1
1
R/W
R/W
R/1W
R/W
R/W
R/W
R/W
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after rese1t
Table 125. SRDS_CLK_CFG Field Descriptions
Bit Field
15
SERDES_CLK_SEL
14:11
10:2
SERDES_REFCLK_DIV
Reserved
1:0 SERDES_REFCLK_PREDIV
Type
R/W
R/W
R/W
Reset
0
0x0
0x000
R/W
10
Description
Select either the PLL output of the DACCLK from the pad.
0 = DACCLK pad
1 = PLL output
The divide amount for the serdes REFCLK
Reserved
These bits select the pre-divide on the DACCLK input clock
before the DACCLK is used in the dividers used in the SERDES
PLL REFCLK and the Fusefarm SYSCLK.
00 = if DACCLK input ≤ 2 GHz; prediv is set to div1
01 = if DACCLK input is ≤ 4 GHz and > 2 GHz, prediv is set to
div2
10 = if DACCLK input is ≤ 9 GHz and > 4 GHz, prediv is set to
div4
11 = Not valid
8.5.85 Serdes PLL Configuration Register (address = 0x3C) [reset = 0x8228]
Figure 136. Serdes PLL Configuration Register (SRDS_PLL_CFG)
15
14
13
12
11
10
9
8
0
0
0
0
0
0
0
x
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
7
6
5
4
3
2
1
0
0
0
1
1
1
1
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Bit
15
14:3
12:11
10
9
8:1
0
Field
ENDIVCLK
CLKBYP
LB
SLEEPPLL
VRANGE
MPY
CORRECT
Table 126. SRDS_PLL_CFG Field Descriptions
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reset
1
00
00
0
1
00010100
0
Description
Enable divided by 5 output clock
Serdes clock bypass
Serdes PLL loop bandwidth
Serdes PLL Sleep
Serdes PLL loop filter range
Serdes reference clock multiply factor
AND'ed with LANE_ENA so it must be set to 1 for correct
behavior
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